The present invention provides an improved optoelectronic transceiver having a signal detect output which can be adapted to any particular logic level required by a host device.
Optoelectronic transceivers are well known in the art. In general, such transceivers are employed to optically transmit and receive data between two or more electronic host devices. To transmit data, the optoelectronic transceiver receives an electrical data signal from its host device, converts the electrical data signal to an optical signal, and transmits the optical signal over a transfer medium such as an optical fiber. On the receive side of the optoelectronic transceiver, optical signals are received over the optical transfer medium and converted into electrical data signals which are communicated to the host device.
The transceiver is usually mounted on or adjacent to the motherboard of the host device. Data communication between the host device and the transceiver is managed by a controller chip such as a Media Access Controller, or MAC, chip. The MAC chip resides on the mother board, and controls the flow of data between the host's processing unit and the transceiver module. Thus all data signals, as well as diagnostic and control signals generated by either the host device or the transceiver module, and relating to the communication of data over the optical data link must be input to the MAC chip so that the controller can act on them accordingly.
One such signal which is commonly generated by optoelectronic transceivers, particularly in 1.times.9 transceiver packages, is an optical signal detected signal or SD. The SD signal is input to the media controller from the transceiver in order to alert the host device that an optical signal is being received. In present generation transceiver modules such as the 1.times.9, the SD signal supplied to the host device is an emitter coupled logic (ECL) or positive emitter coupled logic (PECL) signal. Due to the relatively small voltage difference between logic levels, ECL or PECL are the preferred logic for high speed data communications modules. However, most host devices and media controllers operate using other logic levels such as CMOS or TTL. Thus, there is an interface problem between the ECL or PECL SD signal and the TTL or CMOS level circuitry of the host device.
To date, the interface problem has been resolved by adding an ECL/TTL converter chip (or some other converter chip depending on the particular logic levels being converted) directly to the motherboard of the host device. A converter chip accepts the ECL level SD signal and converts it to a TTL level signal which is then input to the media controller chip. A drawback to this solution, however, is that it adds cost to the production of the motherboard. Another drawback is that the extra semiconductor chip required to convert the ECL level signal to TTL consumes space on the mother board. In most electronic equipment miniaturization is of extreme importance, and real estate on the motherboard comes at a premium. The added converter chip required to adapt the SD signal occupies valuable space which could otherwise be used for additional circuit features to enhance the functionality of the host device.
To avoid this interface problem in a cost effective manner, and to save space on the host device motherboard, an optoelectronic transceiver is needed having an optical signal detected output which has a logic level specifically adapted to the logic level of the media controller with which it will interface. In an improved transceiver module the SD signal should be generated directly at the logic level required, without the need for a converter chip. It is also desirable that the SD output be configurable such that selective placement of external resistors will adapt the SD to a particular logic level. It is even more desirable that such an optoelectronic transceiver module having an adaptable SD output be provided in an 1.times.9 transceiver package wherein the adaptable logic levels include TTL, CMOS, or a high voltage output.